1. Field of the Invention
The invention generally relates to a semiconductor device and method of manufacture and, more particularly, to a semiconductor device having analog, or super thick, wires and a method of manufacturing thereof using a dual-damascene process.
2. Background Description
Super thick damascene copper (Cu) wires (e.g., >2 um thick) are currently fabricated with single damascene processing. The use of a single damascene process is mainly due to integration problems associated with dual-damascene processing, including the problem of contacting both MIM capacitors and underlying wiring layers during the via and wire etching processes.
In the super thick dual-damascene Cu wire processes, the vias and trenches are defined using conventional lithography steps. In these conventional processes, the via is about 5.5. μm in height and at about 1.5 μm in width. After the formation of the via, the via is filled with spin on organic material such as, for example, anti-reflective coating (ARC), to the underlying Cu wiring layer Mx, for a trough lithographic step.
However, it has been found that the second dual-damascene lithography step is difficult to make work in the super thick damascene Cu wire processes. By way of example, for a via first, trench last process, it has been found that the ARC forms an hourglass formation in the via which, in turn, results in large voids in the via. More specifically, it has been found that none of the industry standard mid UV (MUV) or Deep UV (DUV) ARCs achieved more than 40% fill, with all of them leaving large voids in the vias which opened up during trough etch. And, due to these voids, subsequent etching caused corrosion in an underlying metal layer due to the etchant etching through the voids.
If the ARC, for example, is made thicker, there is better fill properties within the via; however, other problems arise during the subsequent etching process. For example, acceptable via fill can be achieved using an 0.8 um layer, but this severely complicates the trough RIE due to the very long ARC open step required, and due to large fences or rails generated around the vias during trough RIE. More specifically, during the RIE process using the thicker ARC fill, fences are formed on the sides of the via, early in the trough RIE process. This leads to preferential etching along the via edges down to an underlying metal (Mx) layer. Thus, it was found that when the ARC is of about 0.8 um, there is resist erosion, massive fencing and trough RIE (reactive ion etching) problems.
The invention is directed to overcoming one or more of the problems as set forth above.